Because of the ongoing need to increase the capacity of memory devices such as dynamic random access memory (DRAM) devices, there is a concomitant need to develop methods of fabricating memory devices having reduced unit cell size. Unfortunately, reducing the unit cell size of a memory device typically results in a reduction in the capacitance of storage capacitors therein and this reduction can be detrimental to the reliability of the memory device (e.g., data retention reliability). Accordingly, techniques to reduce unit cell size typically include steps to preserve capacitance levels by using dielectric materials with high dielectric coefficients and/or by forming capacitor electrodes having threedimensional shapes which preserve overall surface area.
One conventional method of forming a storage capacitor for a unit cell DRAM device is illustrated by FIG. 1. According to this method, an active portion of a semiconductor substrate 2 is defined between adjacent field oxide isolation regions 4. A plurality of insulated gate electrodes 6-11 are also formed on the substrate 2 and these gate electrodes may extend in parallel across an array of memory cells as word lines. Source/drain regions (not shown) may be formed in the active portion of the substrate 2 between adjacent gate electrodes. A first electrically insulating layer 12 (e.g., oxide layer) is also formed on the substrate. First contact holes may be formed in the first electrically insulating layer 12 and these first contact holes may be filled by a plurality of contact plugs (e.g., polysilicon contact plugs) 14-16. A second electrically insulating layer may then be formed on the first electrically insulating layer. This second electrically insulating layer may comprise an oxide layer 18 and a silicon nitride layer 20. Second contact holes 22a and 22b may then be formed in the second electrically insulating layer, as illustrated. Next, a blanket layer of polycrystalline silicon may be deposited on the second electrically insulating layer and in the contact holes. This blanket layer may then be patterned to define a plurality of storage nodes (i.e., lower capacitor electrodes of storage capacitors). Unfortunately, during this patterning step which typically involves etching back the blanket layer to expose the silicon nitride layer 20, an over-etch condition may take place and result in the formation of a reduce area region 25 in the contact hole. The size of this reduced area region may increase as the degree of photolithographic misalignment during the patterning step increases. As will be understood by those skilled in the art, this reduced area region 25 may degrade the electrical characteristics of the storage capacitor.
Accordingly, notwithstanding the above-described method, there continues to be a need for improved methods of forming integrated circuit memory devices.